In integrated circuit technology, digital systems are designed to operate based on clock signals. The clock signals are used to synchronize the operation of different components of the systems. The quality of the clock signals, including frequency, phase, amplitude and duty cycle, affects system performance.
A duty cycle of a clock signal is at 50% when a pulse width of a logic high pulse and a logic low pulse of a clock signal are equal to each other (i.e., have equal time intervals). The pulse widths together represent an operating frequency of the system clock. Systems operate based on the synchronization of rising and falling edges of the clock signal. If the duty cycle of the clock is not equal to 50%, the duty cycle is distorted and a timing of the operation of the components is affected. In some applications, duty cycle distortion affects performance of large scale systems, when adopting aggressive architecture such as double data rate (DDR) data architecture. A duty cycle correction circuit is typically used to adjust the duty cycle to 50%. An existing duty cycle correction method includes over-sampling a clock by using a higher frequency clock to compare the pulse width of the logic high pulse and logic low pulse of a clock signal. Another existing duty cycle correction method includes using a differential driving cell with an analog output integration circuit to differentiate between a pulse width of the logic high pulse and the logic low pulse.